The PLL is widely used in System on Chip (SOC) to construct a frequency synthesizer, a clock generator and so on. FIG. 1 shows a basic structure of a PLL. In FIG. 1, the phase frequency detector (PFD) 10 detects the frequency difference and the phase difference between the input signal Fref and the feedback signal Ffb and generates and inputs pulse control signals UP and DN to the charge pump 20. In the charge pump 20, the pulse control signals UP and DN are converted into current IP so as to discharge and charge the capacitor Cp in the loop filter 30. The loop filter 30 generates the control voltage Vctrl and input the control voltage Vctrl to the voltage control oscillator (VCO) 40. The VCO 40 increases the oscillation frequency when the control voltage Vctrl increases and decreases the oscillation frequency when the control voltage Vctrl decreases. The frequency divider 50 processes the output signal Fout of the VCO 40 to generate the feedback signal Ffb. Thus, a feedback system is formed and the frequency and phase of the output signal Fout is locked to a constant frequency and phase.
The loop bandwidth ωn of the PLL in FIG. 1 may be obtained with formula 1) and the damping factor ξ of the PLL may be obtained with formula 2).
                              ω          n                ⁢                                                            K                v                            ⁢                              I                p                                                    NC              p                                                          1        )                                ξ        =                                            R              p                        2                    ⁢                                                                      I                  p                                ⁢                                  K                  v                                ⁢                                  C                  p                                            N                                                          2        )            In the formulas, Cp represents the capacitance of the loop filter 30, Rp represents the resistance of the loop filter 30, Ip represents the current for charging and discharging the capacitor Cp i.e. the charge and discharge current output from the CP 20, Kv represents the gain of the VCO 40 and N represents the frequency division factor of the frequency divider 50.
The high performance and low jitter PLL should not be susceptive to the change of the process, voltage and temperature (PVT). The ratio of the loop bandwidth ωn of the PLL to the angular frequency ωref of the input signal (referred to as input frequency for short as blew, ωref=2πFref and Fref is the frequency of the input signal) and the damping factor ξ should be constant. Thus, the range of the input frequency is not limited and the loop bandwidth ωn of the PLL may reflect the input frequency of the PLL. In the PLL shown in FIG. 1, when the current Ip output from the charge pump 20, the capacitance of the capacitor Cp in the loop filter 30 and the gain Kv of the VCO 40 are determined, if the resistance Rp of the loop filter 30 or the frequency division factor N of the frequency divider 50 changes, the ratio of the loop bandwidth ωn to the input frequency ωref and the damping factor ξ may not be constant. Therefore, the design for the PLL is constrained.
The self-biased PLL may solve the above problem, in other words, even the resistance of the loop filter or the frequency division factor of the frequency divider changes, the ratio of the loop bandwidth ωn to the input frequency ωref and the damping factor ξ may be kept constant. The reference document “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” (John G Maneatis, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 11, NOVEMBER 1996) discloses a basic structure of the self-biased PLL. As shown in FIG. 2, the loop filter 31 includes a capacitor C1 and a bias generator 60. Particularly, the bias generator 60 establishes the resistance of the loop filter 31, adds a current output from an additional charge pump 21 to the output terminal for outputting the bias voltage VBP in the bias generator 60. Thus, the charge pump 20 charges and discharges the capacitor C1 and the charge pump 21 charges and discharges the resistance established by the bias generator 60.
The bias generator 60 is adapted to generate the bias voltages VBP and VBN from the control voltage VCTRL so as to provide the input voltage of the VCO 41. As shown in FIG. 3, the bias generator 60 includes a bias initiation circuit 601, an amplifier bias circuit 602, a differential amplifier circuit 603, a half-buffer replica circuit 604, a control voltage buffer circuit 605. The amplifier bias circuit provides the bias for the differential amplifier circuit 603 and the differential amplifier circuit 603 adjusts the bias voltage VBN. Thus, the half-buffer replica circuit 604 and the control voltage buffer circuit 605 duplicates the control voltage VCTRL to the output terminal i.e. VBP=VCTRL.
The VCO 41 includes n (n≧3) buffer stages. For example, in FIG. 4, the VCO 41 includes three differential buffer delay stages 410 each with a symmetrical load. The bias voltage VBN provides bias current 2ID (ID represents the current passing through the symmetrical load 411 or 412) for the symmetrical loads 411 and 412. The bias voltage VBP of the symmetrical load 411 or 412 is equivalent to the control voltage VCTRL. The equivalent resistance of the symmetrical load 411 or 412 is ½ gm. gm represents the transconductance of a transistor in the symmetrical load. When the control voltage VCTRL changes, the resistance of the symmetrical load 411 or 412 changes, the delay of the buffer stage changes and the frequency of the output signal (CK+ or CK−) from the VCO 41 also changes.
If the current Ip output from the charge pumps 20 and 21 is x times than the bias current 2ID of the symmetrical loads 411 and 412 and the resistance Rp of the loop filter 31 established by the symmetrical load 606 in the bias generator 60 is y times than the equivalent resistance Ro of the buffer stage 410 in the VCO 41, in other words, if Ip=x·2ID and Rp=yRo=y/2 gm, the ratio of the loop bandwidth ωn of the self-biased PLL to the input frequency ωref may be represented with formula 3) and the damping factor ξ of the loop may be represented with formula 4) as follows.
                                          ω            n                                ω            ref                          =                                            x              ⁢                                                          ⁢              N                                      2              ⁢                                                          ⁢              π                                ⁢                                                    C                B                                            C                1                                                                        3        )                                ξ        =                              y            4                    ⁢                                    x              N                                ⁢                                                    C                1                                            C                B                                                                        4        )            In the formulas, the CB represents the parasitic capacitance of the VCO 41. Therefore, if the parameters x, y and the frequency division factor N are met a certain condition through an appropriate design, the frequency division factor N may be eliminated and thus the ratio of the loop bandwidth to the input frequency ωn/ωref and the damping factor ξ only depend on the values of the capacitance CB and C1 which relate to the fabrication process.
Based on the above structure of the self-biased PLL, John G Maneatis et. al. propose a self-biased PLL (see, “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003) in which the parameters x and y in the formulas 3) and 4) are properly designed. As shown in FIG. 5, through the programmable 1/N current mirror 70, the current IP output from the charge pump 20 and 21 is configured as 1/N times than the bias current of the VCO 41, and the resistance RP of the loop filter 32 is configured as N·CB/C2 times than the equivalent resistance ½ gm of the buffer stage in the VCO 41, in other words, x=1% N and y=N·CB/C2. Thus, the following formulas may be obtained.
                                          ω            n                                ω            ref                          =                                                            x                ⁢                                                                  ⁢                N                                            2                ⁢                                                                  ⁢                π                                      ⁢                                                            C                  B                                                  C                  1                  ′                                                              =                                                                                          1                    N                                    ⁢                  N                                                  2                  ⁢                                                                          ⁢                  π                                            ⁢                                                                    C                    B                                                        C                    1                    ′                                                                        =                                          1                                  2                  ⁢                                                                          ⁢                  π                                            ⁢                                                                    C                    B                                                        C                    1                    ′                                                                                                          5        )                                ξ        =                                            y              4                        ⁢                                          x                N                                      ⁢                                                            C                  1                  ′                                                  C                  B                                                              =                                                                                          NC                    B                                                        C                    2                                                  4                            ⁢                                                                    1                    N                                    N                                            ⁢                                                                    C                    1                    ′                                                        C                    B                                                                        =                                          1                                  4                  ⁢                                                                          ⁢                                      C                    2                                                              ⁢                                                                    C                    B                                    ⁢                                      C                    1                    ′                                                                                                          6        )            In the above formulas, C′1=C1+C2. Thus, the ratio of the loop bandwidth to the input frequency ωn/ωref and the damping factor ξ only depend on the values of the capacitance CB, C1 and C2 which relate to the fabrication process, regardless of the resistance Rp of the loop filter and the frequency division factor N of the frequency divider.
However, in the self-biased PLL shown FIG. 5, a new parameter i.e. capacitance C2 is added to make the parameters x, y and the frequency division factor N meet an appropriate condition, so that the ratio of the loop bandwidth to the input frequency ωn/ωref and the damping factor ξ are independent of the resistance RP of the loop filter and the frequency division factor N of the frequency divider. Moreover, in order to balance the voltage on the capacitor C1 and C2, an additional conversion circuit including a capacitor C2 and a balance switch S is added. Therefore, the complexity of the circuit design is increased.